Low power adiabatic programmable logic array with APDL-2-Reference-Cited by-同舟云学术

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Low power adiabatic programmable logic array with APDL-2

Published:2003 Issue:21 Volume:39 Page:1501
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Yang W.J.,Zhou Y.,Lau K.T.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el_20030994?crawler=true&mimetype=application/pdf

Reference5 articles.

1. Rabaey, J.M., Chandrakasan, A., and Nikolic, B.: ‘Digital integrated circuits—a design perspective’, 2nd(Prentice Hall Electronics and VLSI Series 2003)

2. Adiabatic pseudo-domino logic

3. Adiabatic dynamic logic

4. Pucknell, D., and Eshraghian, K.: ‘Basic VLSI design’, (Prentice Hall 1994)

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2. Comparative Analysis of FinFET and CMOS based Adiabatic ECRL Technique;2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS);2023-06-14

3. Considerations for Ultra-Low-Power VLSI Design—A Survey;Journal of Nanoelectronics and Optoelectronics;2017-01-01

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