6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process
Author:
Affiliation:
1. Department of Electronics & Communication EngineeringNational Institute of Technology GoaGoaIndia
2. Department of Electrical, Computer, and Biomedical EngineeringUniversity of PaviaPaviaItaly
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0421
Reference28 articles.
1. Six‐bit, reusable comparator stage‐based asynchronous binary‐search SAR ADC using smart switching network
2. A 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor
3. Background Digital Calibration of Comparator Offsets in Pipeline ADCs
4. A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals
5. A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC
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