Improved matrix multiplier design for high‐speed digital signal processing applications-Reference-Cited by-同舟云学术

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Improved matrix multiplier design for high‐speed digital signal processing applications

Published:2014-01 Issue:1 Volume:8 Page:27-37
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Saha Prabir¹,Banerjee Arindam²,Bhattacharyya Partha³,Dandapat Anup¹

Affiliation:

1. Department of Electronics and Communication EngineeringNational Institute of TechnologyMeghalayaShillong793003India

2. Department of Electronics and Communication EngineeringJIS College of EngineeringKalyani741235India

3. Department of Electronics and Telecommunication EngineeringBengal Engineering and Science UniversityShibpurHowrah711103India

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2013.0117

Reference27 articles.

1. Design and implementation of a high-speed matrix multiplier based on word-width decomposition

2. Gao S. Al‐Khalili D. Chabini N.: ‘Two level decomposition based matrix multiplication for FPGAs’.Proc. IEEE Int. Conf. Electronics Circuits & Systems December2009 pp.427–430

3. Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system

4. Idris M. Noor N.M. Tamil E.M. Razak Z. Arof H.: ‘Parallel matrix multiplication design for monocular SLAM’.Proc. IEEE Fourth Asia Int. Conf. Mathematical/Analytical Modeling and Computer Simulation (AMS) May2010 pp.492–497

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