Affiliation:
1. State Key Laboratory of Novel Software TechnologyDepartment of Computer Science and TechnologyNanjing UniversityNanjing 210046People's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
General Engineering,Energy Engineering and Power Technology,Software
Reference45 articles.
1. Performance evaluation and design trade‐offs for network‐on‐chip interconnect architectures;Pande P.P.;IEEE Trans. Comput.,2005
2. VangalS. HowardJ. RuhlG.et al.: ‘An 80‐tile 1.28tflops network‐on‐chip in 65 nm cmos’.Proc. IEEE Int. Solid‐State Circuits Conf. February 2007 pp.98–589
3. BellS. EdwardsB. AmannJ.et al.: ‘Tile64 processor: a 64‐core soc with mesh interconnect’.Proc. IEEE Int. Solid‐State Circuits Conf. February 2008 pp.88–598
4. BahnJ.H. LeeS.E. BagherzadehN.: ‘On design and analysis of a feasible network‐on‐chip (noc) architecture’.Proc. Fourth Int. Conf. Information Technology April 2007 pp.1033–1038
5. 3d topologies for networks‐on‐chip;Pavlidis V.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2007
Cited by
24 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献