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Built‐in‐self‐test technique for diagnosis of delay faults in cluster‐based field programmable gate arrays

  • Published:2013-09 Issue:5 Volume:7 Page:210-220
  • ISSN:1751-8601
  • Container-title:IET Computers & Digital Techniques
  • language:en
  • Short-container-title:IET Computers & Digital Techniques

Author:

Das Nachiketa1,Roy Pranab1,Rahaman Hafizur1

Affiliation:

1. School of VLSI TechnologyBengal Engineering and Science UniversityShibpurIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

1. Das N. Roy P. Rahaman H.: ‘Build‐in‐self‐test of FPGA for diagnosis of delay fault’.IEEE ASQED 2011 pp.54–61

2. Das N. Roy P. Rahaman H.: ‘New technique for testing of delay fault in cluster based FPGA’.IEEE MWSCAS 2011 pp.1–4

3. Harris I.G. Menon P.R. Tessier R.: ‘BIST‐based delay path testing in FPGA architectures’.IEEE ITC 2001 pp.932–938

4. Das N. Ghosh S. Rahaman H.: ‘Detection of single stuck‐at and bridging faults in cluster‐based FPGA Architectures’.Proc. VDAT 2007 pp.205–212

5. Das N. Roy P. Rahaman H.: ‘On line testing of single feedback bridging fault in cluster based FPGA by using Asynchronous element’.IEEE IOLTS 2008

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1. A Concurrent Testing Scheme for Muller Circuits Using Reduced Ordered Binary Decision Diagram;2022 IEEE Region 10 Symposium (TENSYMP);2022-07-01

2. Experimental Verification of a New Oscillation-based Test Algorithm for Analog Circuits;IETE Journal of Research;2021-11-02

3. A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements;Journal of Electronic Testing;2019-10

4. A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01
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