Low Ron and high robustness ESD protection design for low‐voltage power clamp application
Author:
Affiliation:
1. Department of Electronics and Electrical EngineeringDankook University126 Jukjeon‐dong, Suji‐guYongin‐siGyeonggi‐doRepublic of Korea
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2016.2391
Reference3 articles.
1. Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
2. High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps
3. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
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