Fractional‐ N PLL with multi‐element fractional divider for noise reduction-Reference-Cited by-同舟云学术

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Fractional‐ N PLL with multi‐element fractional divider for noise reduction

Published:2016-05 Issue:10 Volume:52 Page:809-810
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Sanyal Arindam¹,Yu Xueyi²,Zhang Yanlong³,Sun Nan¹

Affiliation:

1. Department of Electrical and Computer EngineeringThe University of Texas at AustinTXUSA

2. Spintrol Ltd.ShanghaiPeople's Republic of China

3. School of MicroelectronicsThe University of Texas at AustinTXUSA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2016.0680

Reference4 articles.

1. An FIR‐embedded noise filtering method for ΔΣ fractional‐N PLL clock generators;Yu X.;IEEE JSSC,2009

2. A widebandwidth 2.4 GHz ISM‐band fractional‐N PLL with adaptive phase noise cancellation;Swaminathan A.;IEEE JSSC,2007

3. A semidigital dual delay‐locked loop;Sidiropoulos S.;IEEE JSSC,1997

4. High‐order mismatch‐shaping in multibit DACs;Sun N.;IEEE TCAS–II,2011

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1. CMOS analog and mixed-signal phase-locked loops: An overview;Journal of Semiconductors;2020-11-01

2. Current pulse shaping technique for low spur fractional‐N phase‐locked loop;Electronics Letters;2020-03

3. A Fractional-$N$ PLL With Space–Time Averaging for Quantization Noise Reduction;IEEE Journal of Solid-State Circuits;2020-03

4. A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction;2019 IEEE Custom Integrated Circuits Conference (CICC);2019-04

5. CMOS Transmitters for 2.4-GHz RF Devices: Design Architectures of the 2.4-GHz CMOS Transmitter for RF Devices;IEEE Microwave Magazine;2019-01

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