SPICE-compatible modelling technique for simulating floating-gate transistors
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el.2011.0458?crawler=true&mimetype=application/pdf
Reference7 articles.
1. A new compact DC model of floating gate memory cells without capacitive coupling coefficients
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