Area‐efficient parallel adder with faithful approximation for image and signal processing applications-Reference-Cited by-同舟云学术

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Published:2019-10-15 Issue:13 Volume:13 Page:2587-2594
ISSN:1751-9659
Container-title:IET Image Processing
language:en
Short-container-title:IET image process

Author:

Palanisamy Gnanambikai¹^ORCID,Krishnasamy Natarajan Vijeyakumar²,Sundaram Kalaiselvi²

Affiliation:

1. Department of Electronics and Communication EngineeringNachimuthu Polytechnic CollegePollachi642003Tamil NaduIndia

2. Department of Electronics and Communication EngineeringDr. Mahalingam College of Engineering and TechnologyPollachi642003Tamil NaduIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Signal Processing,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-ipr.2019.0580

Reference26 articles.

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3. Design of area and speed efficient square root carry select adder using fast adders;Priyadarshini K.M.;Int. J. Sci. Technol. Res.,2014

4. Carry-select adder using single ripple-carry adder

5. 64-bit carry-select adder with reduced area

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