Low‐complexity twiddle factor generation for FFT processor-Reference-Cited by-同舟云学术

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Low‐complexity twiddle factor generation for FFT processor

Published:2013-11 Issue:23 Volume:49 Page:1443-1445
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Kang Hyeong‐Ju¹,Lee Jong‐Yeol²,Kim Ji‐Hoon³

Affiliation:

1. School of Computer Science and EngineeringKorea University of Technology and EducationCheonanRepublic of Korea

2. Department of Electronic EngineeringChonbuk National UniversityJeonjuRepublic of Korea

3. Department of Electronics EngineeringChungnam National UniversityDaejeonRepublic of Korea

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.2461

Reference7 articles.

1. An algorithm for the machine calculation of complex Fourier series

2. Balanced binary‐tree decomposition for area‐efficient pipelined FFT processing;Lee H.‐Y.;IEEE Trans. Circuits Syst I, Reg. Pprs.,2007

3. Scheme for reducing size of coefficient memory in FFT processor

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1. A Low-footprint FFT Accelerator for a RISC-V-based Multi-core DSP in FMCW Radars;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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3. Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

4. An ultra-long FFT architecture implemented in a reconfigurable application specified processor;IEICE Electronics Express;2016

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