6.8 mW 15 dBm IIP3 CMOS common‐gate LNA employing post‐linearisation technique
Author:
Affiliation:
1. No. 38 Research Institute of CETCHefeiPeople's Republic of China
2. Department of Communication and Information EngineeringUESTCChengduPeople's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.3442
Reference7 articles.
1. Modified derivative superposition method for linearizing FET low-noise amplifiers
2. Post‐linearization of cascode CMOS LNA using folded PMOS IMD sinker;Kim T.‐S.;IEEE Microw. Wirel. Compon. Lett.,2006
3. A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA
4. Analysis and design of configurable LNAs in feedback common‐gate topologies;Liscidini A.;IEEE Trans. Circuits Syst. II, Express Briefs,2008
5. A Common-Gate Amplifier With Transconductance Nonlinearity Cancellation and Its High-Frequency Analysis Using the Volterra Series
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