High-performance single clock cycle CMOS comparator
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20063083?crawler=true&mimetype=application/pdf
Reference3 articles.
1. 1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking
2. High-performance and power-efficient CMOS comparators
3. High-speed and low-power CMOS priority encoders
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2. Efficient Dynamic Logic Magnitude Comparators;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03
3. Modified priority encoder based hardware efficient N-bit comparator;International Journal of Electronics Letters;2022-09-02
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