A graphical technique of controller design and selection of lower and upper bounds in controller design using optimization techniques

Author:

Ahamad Nafees1,Chhetri Abhay1,Saklani Mayank1,Bajaj Mohit234ORCID,Kotb Hossam5,Khan Baseem6ORCID,Sikander Afzal7

Affiliation:

1. Department of Electrical and Electronics & Communication Engineering DIT University Dehradun Uttarakhand India

2. Department of Electrical Engineering Graphic Era (Deemed to be University) Dehradun India

3. Graphic Era Hill University Dehradun India

4. Applied Science Research Center Applied Science Private University Amman Jordan

5. Department of Electrical Power and Machines, Faculty of Engineering Alexandria University Alexandria Egypt

6. Department of Electrical and Computer Engineering Hawassa University Hawassa Ethiopia

7. Department of Instrumentation and Control Engineering Dr. B. R. Ambedkar National Institute of Technology Jalandhar Jalandhar Punjab India

Abstract

AbstractThe regulation and stabilization of a system's output to achieve desired performance and ensure system reliability require the use of different controllers, but selecting appropriate control parameters presents a challenge in ensuring robustness and stability. Proportional–integral–derivative (PID) controllers are popularly used due to their simplicity and effectiveness in addressing these challenges. In this paper, a simple, effective, and efficient, novel graphical technique is proposed to design PID and its variants (PI/PD) controllers, which addresses the challenges in selecting appropriate control parameters. The method involves creating three equispaced vectors for controller parameters , and obtaining a 3D (2D in PI/PD) Cartesian grid of these vectors. All nodes in the grid provide several possible controllers, and integral time squared error (ITSE) is calculated for each controller from the closed‐loop step response of the system. The obtained ITSE is plotted in a 4D (PID) or 3D (PI/PD) graph, and controller parameters corresponding to the minimum value of ITSE are identified. Furthermore, the proposed graphical technique aids in choosing the lower and upper bounds (LB and UB) if the controller is designed using optimization techniques. The better selection of LB and UB reduces the search space resulting in lesser execution time and fewer iterations. To validate the proposed graphical technique, we designed various controllers for widely‐used brush‐less DC and switch reluctance motors in electric vehicles. Additionally, by choosing the LB and UB with the proposed technique, controllers are also designed using three optimization techniques: particle swarm optimization, black widow optimization algorithm, and honey badger algorithm. The obtained controllers using the graphical technique outperformed the optimization techniques in terms of time and frequency domain specifications, and the proposed selection of lower and upper bounds resulted in improved performance in terms of iterations and execution time.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Optimization,Computer Science Applications,Human-Computer Interaction,Control and Systems Engineering

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