FPGA implementation of impedance‐compensated phase‐locked loop for HVDC converters
Author:
Affiliation:
1. University of ManitobaWinnipegCanada
2. Teshmont Consultants LPWinnipegCanada
Publisher
Institution of Engineering and Technology (IET)
Subject
General Engineering,Energy Engineering and Power Technology,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/joe.2018.8789
Reference15 articles.
1. Impedance‐compensated grid synchronisation for extending the stability range of weak grids with voltage source converters
2. Ajinai: ‘Improved HVDC Dynamic Performance via Phase Locking to Virtual Thévenin Voltage’. MS.c thesis University of Manitoba 2017
3. Advanced Control of Induction Motor Based on Load Angle Estimation
4. Design of a Real-Time Digital Simulator for a D-STATCOM System
5. Word length selection method based on mixed simulation for digital PID controllers implemented in FPGA;Urriza I.;IEEE Int. Symp. Ind. Electron.,2008
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