Complementary logic with 60 nm poly gate JFET for 0.5 V operation-Reference-Cited by-同舟云学术

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Complementary logic with 60 nm poly gate JFET for 0.5 V operation

Published:2010 Issue:11 Volume:46 Page:783
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Kapoor A.K.,Zhang W.,Sonkusale S.,Liu Y.,Gregory P.,Sridharan U.C.,Stager C.,Eib N.,Xie Z.,Vora M.,Prasad J.,Thummalapally D.,Chou R.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el.2010.0742?crawler=true&mimetype=application/pdf

Reference6 articles.

1. Device physics and technology of complementary silicon MESFET's for VLSI applications

2. Medici Users Manual, 2008, www.synopsys.com

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1. 350°C Operation of SiC Complementary JFET Logic Gates;2023 IEEE CPMT Symposium Japan (ICSJ);2023-11-15

2. C-JFET OpAmp on “Folded” Cascode with Compensation Channel for the Systematic Component of the Zero Bias Voltage;2022 Moscow Workshop on Electronic and Networking Technologies (MWENT);2022-06-09

3. SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation;Materials Science Forum;2019-07

4. CJM: A Compact Model for Double-Gate Junction FETs;IEEE Journal of the Electron Devices Society;2019

5. High-Temperature Operation of n- and p-Channel JFETs Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate;IEEE Electron Device Letters;2018-05

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