On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials-Reference-Cited by-同舟云学术

On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials

Published:2018-09 Issue:5 Volume:3 Page:36-44
ISSN:2415-6698
Container-title:Advances in Science, Technology and Engineering Systems Journal
language:
Short-container-title:Adv. sci. technol. eng. syst. j.

Author:

Vais Abhitosh,Sioncke Sonja,Franco Jacopo,Putcha Vamsi,Nyns Laura,Hernandez Arturo Sibaja-,Rooyackers Rita,Ardila Sergio Calderon,Spampinato Valentina,Franquet Alexis,Maes Jan,Xie Qi,Givens Michael,Tang Fu,Jiang Xiang,Heyns Marc,Linten Dimitri,Mitard Jerome,Thean Aaron,Mocuta Dan,Collaert Nadine

Publisher

ASTES Journal

Subject

Management of Technology and Innovation,Physics and Astronomy (miscellaneous),Engineering (miscellaneous)

Link

https://www.astesj.com/publications/ASTESJ_030506.pdf

Reference12 articles.

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2. A. Vais, A. Alian, L. Nyns, J. Franco, S. Sioncke, V. Putcha H. Yu, Y. Mols, R. Rooyackers, D. Lin, J.W. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, A. Mocuta, N. Collaert, K. De Meyer, A. Thean, "Record mobility (µeff~ 3100 cm2/Vs) and reliability performance (Vov~ 0.5 V for 10yr operation) of In0.53Ga0. 47As MOS devices using improved surface preparation and a novel interfacial layer" in IEEE Symposium on VLSI Technology, pp. 140-141. 2016. https://doi.org/10.1109/VLSIT.2016.7573410

3. C. B. Zota, F. Lindelöw, L.-E. Wernersson, and E. Lind. "InGaAs nanowire MOSFETs with ION= 555 µA/µm at IOFF= 100 nA/µm and VDD= 0.5 V" in IEEE Symposium on VLSI Technology, pp. 1-2. IEEE, 2016. https://doi.org/10.1109/VLSIT.2016.7573418

4. N. Waldron, S. Sioncke, J. Franco, L. Nyns, A. Vais, X. Zhou, H. C. Lin, G. Boccardi, J. W. Maes, Q. Xie and M. Givens, F. Tang , X. Jiang , E. Chiu, A. Opdebeeck, C. Merckling, F. Sebaai, D. van Dorp, L. Teugels, A. Sibaja Hernandez, K. De Meyer, K. Barla, N. Collaert, A. Thean, "Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200 μS/μm at 50 nm Lg using a replacement Fin RMG flow" in IEEE International Electron Devices Meeting (IEDM), pp. 31-1. IEEE, 2015. https://doi.org/10.1109/IEDM.2015.7409805

5. R. Suzuki, N. Taoka, M. Yokoyama, S. Lee, S. H. Kim, T. Hoshii, T. Yasuda, W. Jevasuwan, T. Maeda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, " 1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density," Appl. Phys. Lett. 100(13), 132906-1-132906-3 (2012). https://doi.org/10.1063/1.3698095.

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1. Characterization of High-Performance InGaAs QW-MOSFETs With Reliable Bi-Layer HfOxNy Gate Stack;IEEE Journal of the Electron Devices Society;2019