A High Accuracy Sample and Hold Circuit with Reduced Non-Linearity Errors for SAR ADC in 45nm CMOS process-Reference-Cited by-同舟云学术

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A High Accuracy Sample and Hold Circuit with Reduced Non-Linearity Errors for SAR ADC in 45nm CMOS process

Published:2019 Issue: Volume: Page:
ISSN:1556-5068
Container-title:SSRN Electronic Journal
language:en
Short-container-title:SSRN Journal

Author:

Velagaleti Silpa kesav,K.S. Nayanathara,B.K Madhavi

Publisher

Elsevier BV

Reference15 articles.

1. A high-speed fully differential current switch;L Luh;IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process,2000

2. Modelling charge injection in MOS analog switches;B J Sheu;IEEE Trans. Circuits Syst,1947

3. Bootstrapped low-analog switches;J Steensguard;Proc.IEEE-ISCAS Symposium on Circuit and Systems, VLSI,1999

4. Design for Reliability of Low-voltage Switched-capacitor Circuits;A M Abo;Design of Analog CMOS Integrated Circuit,1999

5. Charge Injection in Analog MOS Switches;G Wegmann;CMOS CIRCUIT DESIGN, LAYOUT AND SIMULATION,1987

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Toward Accurate Analysis of Channel Charge Injection in SAR ADCs' Capacitive DACs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Design considerations of high linear SAR-ADC for wireless implantable systems;Materials Today: Proceedings;2020-11

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