Hardened Latch Designs Based on the Characteristic of Transistor for Mitigating Multiple-Node-Upsets in Harsh Radiation Environments-Reference-Cited by-同舟云学术

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Hardened Latch Designs Based on the Characteristic of Transistor for Mitigating Multiple-Node-Upsets in Harsh Radiation Environments

Published:2023 Issue: Volume: Page:
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Author:

Xu Hui,Liu Chaoming,Ma Ruijun,Song Tai,Huang Zhengfeng,Wang Jun,Qin Xuewei,Xia Yu

Publisher

Elsevier BV

Reference24 articles.

1. Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments;A Yan;IEEE Trans Emerg Top Com,2022

2. An advanced SEU tolerant latch based on error detection;J Xu;J Semicond,2018

3. A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design;Y Lu;J Electron Test,2022

4. Design of node separated triple-nodeupset self-recoverable latch;Z Huang;Microelectron J,2021

5. DIRT latch: A novel low cost double node upset tolerant latch;Kiamal Pekmestzi;Microelectron Reliab,2017

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