Design and Simulation Analysis of NWFET for Digital Application

Author:

Bala Shashi1,Kumar Raj2ORCID,Singh Jeetendra3,Sharma Sanjeev Kumar4

Affiliation:

1. Chandigarh Engineering College, Landran, India

2. University Institute of Engineering and Technology, Panjab University, Chandigarh, India

3. National Institute of Technology, Sikkim, India

4. National Institute of Engineering and Technology, Jalandhar, India

Abstract

This chapter presents the design and simulation analysis nanowire-based FET (NWFET) for best possible Ig-Vgs characteristics. A NWFET is a device in which channel is wire-like structure with diameter or lateral dimension in nanometer (10-9 m) range. Performance analysis has been done for various design and process parameters variation to propose optimized parameter for best performance. Although a lot of focus has been put on homogenous Si based NWFETs, there has been a rising interest in III-V NWFETs. This is mainly due to the excellent carrier transport properties are provided by these materials. NWFETs have ability to suppress SCEs and are also good in suppressing OFF-current (IOFF), because of gate all around (GAA) configuration. Secondly, NWFETs have large ON-current (ION) due to quasi one-dimensional (1D) conduction of NWs, and as a result of low carrier scattering, conduction of NWs-based devices is very large.

Publisher

IGI Global

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