Affiliation:
1. National Engineering School of Sousse, Tunisia
Abstract
As power dissipation and time constraint have become vital challenges during the creation of a digital circuit, researchers' and designers' efforts have increased to figure out new ways of preserving power through the study of its sources and its impacts as well as through the decrease of response time to obtain faster treatments. However, it is widely acknowledged that these two parameters are antagonistic in synchronous systems. In fact, current technologies have managed to further decrease the response time to have a faster circuit at the cost of a considerable simultaneous augmentation in its power or vice versa, which leaves no option for designers but to choose from these two important parameters. Hence, the main objective of this chapter is to propose a design method that simultaneously builds a low power design and provides a faster circuit. For the achievement of that purpose, a controller based on a finite state machine (FSM) has been chosen as an example of synchronous system to prove that the new proposed design can optimize both parameters: time and power.
Reference60 articles.
1. Aboushady, H., Dumonteix, Y., Louerat, M. M., & Mehrez, H. (2000). Efficient polyphase decomposition of Comb decimation filters in/spl Sigma//spl Delta/analog-to-digital converters. In Circuits and Systems, 2000.Proceedings of the 43rd IEEE Midwest Symposium on (Vol. 1, pp. 432-435). IEEE.
2. Lowpower design of multipliers using a full-adder isolation technique
3. Dynamic Voltage and Frequency Scaling‐aware dynamic consolidation of virtual machines for energy efficient cloud data centers
4. Novel low-overhead operand isolation techniques for low-power datapath synthesis