Effects of Wafer Cleaning on the Interconnect Structure and Its Electrical Properties during the Al Dual Damascene Process for the Fabrication of Sub-100 nm Memory Devices
Author:
Affiliation:
1. Corporate Research and Development, LG Chem, Ltd.
2. Memory Research and Development Division, Hynix Semiconductor Inc.
3. Department of Chemical Engineering, Ajou University
Publisher
Society of Chemical Engineers, Japan
Subject
General Chemical Engineering,General Chemistry
Link
http://www.jstage.jst.go.jp/article/jcej/38/11/38_11_922/_pdf
Reference8 articles.
1. Frank, W. E.; “Approaches for Patterning of Aluminum,” Microelectron. Eng., 33, 85–100 (1997)
2. Corrosion in Aluminum Chemical Mechanical Planarization for Sub-Quarter-Micron Dynamic Random Access Memory Devices
3. Effect of Etching Process Deviations and Photoresist Stripping on Contact Yield of Copper Dual Damascene Metallization
4. Schnabel, R. F., L. A. Clevenger, G. Costrini, D. M. Dobuzinsky, R. Filippi, J. Gambino, G. Y. Lee, R. C. Iggluden, C. Lin, Z. G. Lu, X. J. Ning, R. Ramachandran, M. Ronay, D. Többen and S. J. Weber; “Aluminum Dual Damascene Metallization for 0.175 μm DRAM Generations and Beyond,” Microelectron. Eng., 50, 265–270 (2000)
5. Multilevel Aluminum Dual-Damascene Interconnects for Process-Step Reduction in 0.18 µm ULSIs
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