Analysis of Decoupling Capacitor Performance in Improving Power Integrity in Two Layer/Three Layer Printed Circuit Boards

Abstract

Electronic circuits can only function properly if supplied with clean power. The clean power is only possible if the AC. & D.C. noise in the power supply voltage which is supplied to electronic devices is below tolerance limits. To keep this noise within the limits, the impedance of Power Distribution Network (PDN) should be as minimal as possible. The use of Decoupling Capacitors is the most proven strategy to keep the PDN impedance low. In this paper, an attempt has been made to analyze the performance of PDN of a two-layer and three-layer P.C. Board, for the same set of Decoupling Capacitors. The PDN design has been carried out to meet an assumed set of specifications. The values of Interconnection Inductance have been obtained. The Interconnection Inductance is mostly responsible for PDN impedance, especially at higher frequencies. The simulations have been conducted for the PDN impedance of a two-layer as well as a three-layer P.C. Board. From the simulated impedance profiles, it is evident that PDN impedance obtained for a two-layer P.C. board is almost similar to that of a three-layer one if the width of the power supply trace is suitably tailored. It is therefore more prudent to go for a two-layer PDN configuration considering its simplicity and economy.