A binary neural computing unit with programmable gate using SFQ and CMOS hybrid circuit

Abstract

Abstract Superconducting neural networks hold significant potential for future applications such as natural language processing and image recognition. To this end, we propose a binary neural computing unit implemented using a hybrid circuit of cryogenic CMOS and superconducting technologies. It offers two main advantages: firstly, we utilize current-mode computations for neural unit weight calculations, significantly reducing the unit’s footprint and enabling the potential for higher integration in the future. Secondly, all computations are performed in a low-temperature environment, which implies the possibility of on-chip learning in superconducting neural networks and the potential for achieving faster training rates in the future. We fabricated the chip using Nb 1 kA cm−2 process (1KP) technology and experimentally verified the correctness of the circuit logic. The margins for various control parameters of the circuit are approximately around 30%, and the superconducting circuit power consumption is estimated to be around 4 microwatts.