Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate

Author:

Sivasubramani SanthoshORCID,Mattela Venkat,Pal Chandrajit,Acharyya AmitORCID

Funder

Redpine Signals Inc., USA

National Post Doctoral Fellowship, SERB, Government of India (GOI)

Visvesvaraya Young Faculty Fellowship Award from the Ministry of Electronics and Information Technology (MEITY), GOI.

Publisher

IOP Publishing

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Mechanics of Materials,General Materials Science,General Chemistry,Bioengineering

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Nano-Magnetic Logic based Architecture for Edge Inference using Tsetlin Machine;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

3. Graphene-based area efficient power planning architecture design methodology for nanomagnetic logic implementation;The Journal of Supercomputing;2023-06-17

4. Novel approach for the design of efficient full adder in MQCA;The Journal of Supercomputing;2022-12-08

5. Beyond CMOS;2021 IEEE International Roadmap for Devices and Systems Outbriefs;2021-11

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