TEM investigations of gate-all-around nanowire devices
Author:
Publisher
IOP Publishing
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://iopscience.iop.org/article/10.1088/1361-6641/ab4b8b/pdf
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1. Overcoming scaling barriers through design technology CoOptimization
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4. Investigation of FinFET Devices for 32nm Technologies and Beyond
5. Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition
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1. Automated (S)TEM metrology characterization of gate-all-around and 3D NAND devices;Metrology, Inspection, and Process Control XXXVII;2023-04-27
2. Stress in Silicon–Germanium Nanowires: Layout Dependence and Imperfect Source/Drain Epitaxial Stressors;IEEE Transactions on Electron Devices;2021-11
3. Development of a robust fabrication process for single silicon nanowire-based omega gate transistors on polyamide substrate;Semiconductor Science and Technology;2020-12-11
4. Preface for the special issue on Microscopy of Semiconducting Materials 2019;Semiconductor Science and Technology;2020-10-13
5. Combined STEM-EDS tomography of nanowire structures;Semiconductor Science and Technology;2019-10-16
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