Low energy non-volatile look-up table using 2 bit ReRAM for field programmable gate array

Abstract

Abstract A low energy non-volatile look-up table (NV-LUT) consisting of 2 bit resistive random-access memories (2 bit ReRAMs) for field-programmable gate arrays (FPGAs) is investigated in this paper. The multi-bit (MB) LUT configuration reduces the number of array cells by half compared to single-bit (SB) ReRAM-based arrays. A comparison of WRITE and READ delay time, energy consumption, and energy delay product (EDP) is carried out between the SB-NVLUT and MB-NVLUT. Different 2, 4, 6, and 8-input LUT configurations were compared. For WRITE 0 and 1 conditions, the MB-NVLUT is 2× faster than the SB-NVLUT and has an average of 1.22× and 2× lower energy consumption and 2.46× and 4.6× lower EDP respectively. For 01 → 10 switching, the MB-NVLUT write delay remains 2× quicker while having 1.03× lower energy consumption and 2.05× lower EDP. The MB-NVLUT is 9.2× lower in write delay, 128× lower in energy consumption, and 153× lower in EDP compared to the SB-NVLUT in 10 → 01 switching. SB-NVLUTs and MB-NVLUTs are then evaluated on Virtex 4 and Virtex 5 FPGA benchmark circuits with the average EDP for SB-NVLUTs greater than that of the MB-NVLUTs and both NVLUTs demonstrating performance matching conventional static RAM LUTs. A LUT controller circuit specifically designed for MB-NVLUT arrays is proposed. The reduction in the MB-NVLUT array cells leads to reduction in components in the controller circuit and improved performances over SB-NVLUTs.