A 1.3V 12-bit 100-MHz Current-Steering DAC in 55nm Technology

Abstract

Abstract In this paper, a 12-bit 100MS/s digital-to-analog converter (DAC) is presented, where a segmented current steering technique is employed. A “4+8” segmented architecture is used compromising the advantages and disadvantages of binary-weighted and thermometer-coded DACs. Cascode current source and cascode switch is used to achieve high input impedance and to minimize output glitches for good linearity and dynamic performance. The simulation results show that SFDR is over 77 dB, and the ENOB is 11.6 bit at least. The DAC consumes 2.27 mW from a 1.3-V supply.