Forming small junctions with reduced defectiveness

Abstract

Abstract This paper is dedicated to studying possibilities of forming small junctions with reduced defectiveness. As horizontal dimensions of devices in VLSIs diminishes, the task of reducing their vertical dimension becomes more pressing. Due to that, the task of producing small p+n junctions for CMOS structures by means of boron implantation becomes ever more important; the projected path of boron ions is significantly longer than those of n-type conductivity dopants. Using ion implantation for this purpose at low energy is not a good idea, as the depth of junction is largely determined by channeling effects in monocrystalline substrates. Ion implantation in substrate covered with amorphous films of SiO2 or Si3N4 does not remove the phenomenon of channeling completely. Nitrogen and oxygen atoms being trapped in the substrate from the amorphous films may result in degradation of characteristics of produced devices. Besides the channeling effects, the processes of dopant redistribution during annealing may also significantly affect the depth of the junctions.