An Output-Capacitorless LDO regulator with fast transient response and high PSRR

Abstract

Abstract A fast transient response and high supply voltage rejection ratio (PSRR) output-capacitor-less low-dropout (OCL-LDO) regulator with a dual power transistor structure is proposed in this paper. The designed flip voltage follower (FVF) structure and the proposed back-gate control loop improve the transient performance of the system. The proposed PSRR enhancement circuit transmits the power supply voltage fluctuation 1:1 to the gate of the power transistor so that the influence of the power supply voltage fluctuation on the output voltage of the LDO is offset by the difference between the gate and source voltages of the power transistor. The simulated results have shown that the proposed OCL-LDO regulator achieves full range stability from 100 μA to 50 mA. The output voltage undershoot is reduced by more than 100 mV when the load current is stepped from 1 to 50 mA in 500 ns without the load capacitor. The PSRR enhancement circuit increases the PSRR of the LDO from 1 KHz to 10 MHz by more than 20 dB.