Razor flip-flop based Detector/Corrector System for Correcting Timing violations in Digital Circuits

Abstract

Abstract In a flip flop, the difference in time between transitions of data input and the active edge of the clock is called its setup time. If the data input changes during this time window, the storage will not be correct. This is called setup time violation. Hold time is the minimum time during which data must be stable after the active edge of the clock. Hold time violation will cause incorrect data storage. The objective of the paper is to design an efficient Detector/Corrector system that monitors and corrects any setup/hold time violations. A Razor flipflop based Detector circuit is proposed in this paper. The Detector block compares data and clock to produce an error signal which in turn makes the Corrector block to correct the clock that assures the desired setup/hold time. The system avoids the setup/hold time violations by simply inverting the clock signal timing. The system is tested using the following digital circuits: ISCAS89 S27 benchmark circuit and a 2×1 multiplexer. Simulation is done using Cadence Virtuoso with 180nm technology. The results are analyzed with existing and proposed detector/corrector systems. The results show that the proposed detector/corrector system is capable of correcting both the setup/hold time violations and also has lesser power consumption when compared with the existing system.