Enhancement of f MAX of InP-based HEMTs by double-recessed offset gate process

Abstract

A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain–source current (I D,max) and maximum extrinsic transconductance (g m,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (f MAX) by reducing drain output conductance (g ds) and drain to gate capacitance (C gd). In addition, further improvement of f MAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of C gd to source to gate capacitance (C gs) by extending drain-side recess length (L rd). Compared with the single-recessed HEMTs, the f MAX of double-recessed offset gate HEMTs was increased by about 20%.