Dynamic sample rate acquisition system based on time-to-digital converter technology

Abstract

Abstract In this paper, we propose a novel acquisition system, which can flexibly adjust the sampling rate according to different sampling requirements. First, we propose a sampling model and conduct feasibility verification experiments on it. The experimental results show that the sampling principle has excellent sampling function. Subsequently, we successfully implemented the system. The system combines the differential comparator of Field-Programmable Gate Array (FPGA) with the characteristics of Time-to-digital converter (TDC), which makes full use of the hardware resources of FPGA to realize efficient digital sampling and reconstruction of unknown signals. Among them, the TDC we designed has a time error of less than 100 ps at sampling rates lower than 50 MSps the sampled signal is transmitted via Ethernet, and the measured on-chip data link throughput rate reaches 600 Mbps the sampled information is decoded, fitted and reconstructed in the host computer. In addition, we have thoroughly studied the factors affecting the sampling quality in this acquisition method and summarized the sampling laws after acquiring multiple signals. To ensure the minimum distortion rate, we choose the threshold signal amplitude as 0–5 times of the highest amplitude of the sampled signal, and select the frequency as 10–30 times. Regarding the system resource consumption, the LUT utilization rate is 12.22%, the Slice utilization rate is 23.37%, and the overall design power consumption is 2.094 W. After a comprehensive evaluation of the performance and comparison with the literature (Kalisz et al 1997 IEEE Trans. Instrum. Meas. 46 51–55), it can be concluded that the system has the advantages of small error, high accuracy, and dynamic sampling function. Summarizing this paper, the system shows good engineering practicability and feasibility in the measurement field.