Optimizing energy efficiency of CNN-based object detection with dynamic voltage and frequency scaling

Author:

Jiang Weixiong,Yu Heng,Zhang Jiale,Wu Jiaxuan,Luo Shaobo,Ha Yajun

Abstract

Abstract On the one hand, accelerating convolution neural networks (CNNs) on FPGAs requires ever increasing high energy efficiency in the edge computing paradigm. On the other hand, unlike normal digital algorithms, CNNs maintain their high robustness even with limited timing errors. By taking advantage of this unique feature, we propose to use dynamic voltage and frequency scaling (DVFS) to further optimize the energy efficiency for CNNs. First, we have developed a DVFS framework on FPGAs. Second, we apply the DVFS to SkyNet, a state-of-the-art neural network targeting on object detection. Third, we analyze the impact of DVFS on CNNs in terms of performance, power, energy efficiency and accuracy. Compared to the state-of-the-art, experimental results show that we have achieved 38% improvement in energy efficiency without any loss in accuracy. Results also show that we can achieve 47% improvement in energy efficiency if we allow 0.11% relaxation in accuracy.

Publisher

IOP Publishing

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference39 articles.

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HSCONN: Hardware-Software Co-Optimization of Self-Attention Neural Networks for Large Language Models;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

2. Performance models and energy-optimal scheduling of DNNs on many-core hardware with dynamic power management;Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI;2023-09-21

3. ARADA;Proceedings of the 20th ACM International Conference on Computing Frontiers;2023-05-09

4. Terminator on SkyNet;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

5. FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-04

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