Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking-Reference-Cited by-同舟云学术

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Effective Cu Filling Method to TSV for 3-dimensional Si Chip Stacking

Published:2012-02-05 Issue:2 Volume:50 Page:152-158
ISSN:1738-8228
Container-title:Korean Journal of Metals and Materials
language:
Short-container-title:Korean J. Met. Mater.

Author:

Publisher

The Korean Institute of Metals and Materials

Subject

Metals and Alloys,Surfaces, Coatings and Films,Modelling and Simulation,Electronic, Optical and Magnetic Materials

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process;Metals;2021-10-19

2. Three-Dimesnional Semicondoctor Stacking using TSV(Through-Si-Via) Technology;Journal of Welding and Joining;2021-06-30

3. A review of soft errors and the low α-solder bumping process in 3-D packaging technology;Journal of Materials Science;2017-07-28

4. Effects of post-annealing and temperature/humidity treatments on the interfacial adhesion energy of the Cu/SiNxinterface for Cu interconnects;Japanese Journal of Applied Physics;2016-05-09

5. Effect of thermal shock on Cu extrusion of TSV for three-dimensional packaging;Korean Journal of Metals and Materials;2014-06-05

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