Design of double edge-triggered flip-flop with low power consumption

Abstract

As is well known, the power consumption of integrated circuits (ICs) is considered one of the most important problems for high-performance chips. Accordingly, for any chip design, power consumption has to be taken into account very seriously. In this paper, a low-power double edge-triggered (DET) D-type flip-flop circuit is proposed. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit, and hence requires a small area. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.