1. Marinissen, E.J., Challenges in Embedded Memory Design and Test, Proceedings of Design, Automation & Test in Europe, 2005, pp. 722–727.
2. Goor, A.J., Testing Semiconductor Memory, Theory and Practice, UK, Chichester: John Wiley & Sons, 1991.
3. Yarmolik, V.N., Murashko, I.A., Kummert, A., and Ivanyuk, A.A., Nerazrushayushchee testirovanie zapominayushchikh ustroistv (Non-Destroying Testing of Memory Devices), Minsk: Bestprint, 2005.
4. Nicolaidis, M., Transparent BIST for RAMs, Proceeding International Test Conference, Baltimore, MD, USA, September 1992, pp. 598–607.
5. Hellebrand, S., Wundelich, Y.-J., and Yarmolik, V.N., Symmetric Transparent BIST for RAMs, Proceedings of Design, Automation & Test in Europe, 1999, pp. 702–707.