FPGA Based Low Area Multi-bit Adjacent Error Correcting Codec for SRAM Application
Author:
Publisher
Allerton Press
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.3103/S0735272720100040.pdf
Reference21 articles.
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3. A. Neale, M. Jonkman, M. Sachdev, "Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs," IEEE Trans. Circuits Syst. II Express Briefs, v.62, n.4, p.387 (2015). DOI: https://doi.org/10.1109/TCSII.2014.2368262.
4. A. Neale, Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs (University of Waterloo, 2014).
5. A. Neale, M. Sachdev, "A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory," IEEE Trans. Device Mater. Reliab., v.13, n.1, p.223 (2013). DOI: https://doi.org/10.1109/TDMR.2012.2232671.
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