1. Naveen Verma, Anantha P. Chandrakasan, “A 65nm 8T sub-Vt SRAM employing sense-amplifier redundancy,” IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers, 11–15 Feb. 2007, San Francisco, CA (IEEE, 2007), pp. 328–606, DOI: 10.1109/ISSCC.2007.373427.
2. Niklas Lotze, Yiannos Manoli, “A 62mV 0.13µm CMOS standard-cell-based design technique using schmitt-trigger logic,” Proc. of IEEE Int. Conf. on Solid-State Circuits, 20–24 Feb. 2011, San Francisco, CA (IEEE, 2011), pp. 340–342, DOI: 10.1109/ISSCC.2011.5746345.
3. Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios Papaefthymiou, “Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic,” IEEE Trans. Very Large Scale Integration (VLSI) Systems 20, No. 6, 977 (Jun. 2012), DOI: 10.1109/TVLSI.2011.2140346.
4. Yingchieh Ho, Chiachi Chang, Chauchin Su, “Design of a subthreshold-supply bootstrapped CMOS inverter based on an active leakage-current reduction technique,” IEEE Trans. Circuits Syst. II: Express Briefs 59, No. 1, 55 (Jan. 2012), DOI: 10.1109/TCSII.2011.2174674.
5. A. Wang, A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits 40, No. 1, 310 (Jan. 2005), DOI: 10.1109/JSSC.2004.837945.