Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes
Author:
Affiliation:
1. Department of Circuit Theory, FEE CTU in Prague, Technicka 2, 16627, Prague, Czech Republic
2. ASICentrum, a company of the Swatch Group, Novodvorska 994, 14221, Prague, Czech Republic
Abstract
Publisher
Walter de Gruyter GmbH
Subject
Instrumentation,Biomedical Engineering,Control and Systems Engineering
Reference8 articles.
1. [1] Dickson, J.F. (1976). On-Chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits, 11 (3), 374-378.
2. [2] Pan, F., Samaddar, T. (2006). Charge Pump Circuit Design. McGraw-Hill Education.
3. [3] Palumbo, G., Pappalardo, D. (2010). Charge pump circuits: An overview on design strategies and topologies. IEEE Circuits and Systems Magazine, 10 (1), 31-45.
4. [4] Matousek, D. (2014). Comparison of selected architectures of negative Charge Pumps with new design. In Radioelektronika : 24th International Conference, April 15-16, 2014. IEEE.
5. [5] Yamazoe, T., Ishida, H., Nihongi, Y. (2009). A Charge Pump that generates positive and negative high voltages with low power-supply voltage and low power consumption for non-volatile memories. In International Symposium on Circuits and Systems (ISCAS 2009), May 24-27, 2009. IEEE, 988-999.
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