Analytical Model of Gate to Channel Capacitance for Nanoscale MOSFETs-Reference-Cited by-同舟云学术

Analytical Model of Gate to Channel Capacitance for Nanoscale MOSFETs

Published:2018-08-29 Issue:5 Volume:66 Page:608-616
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Chatterjee Arun Kumar¹^ORCID,Prasad B.²

Affiliation:

1. Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, (formerly known as Thapar University), Patiala, Punjab, India

2. Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2018.1510746

Reference26 articles.

1. Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices

2. Y. Ma, L. Liu, L. Tian, and Z. Li, “Statistical analysis of quantized inversion layer in MOS devices with ultra-thin gate oxide and high substrate doping levels,” in Proceedings 2000 IEEE Hong Kong Electron Devices Meeting, 2000, pp. 126–9.

3. A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs

4. Determination of the inversion-layer thickness from capacitance measurements of metal-oxide-semiconductor field-effect transistors with ultrathin oxide layers

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