A New Scheme For Cache Coherence In Multiprocessor Systems
Author:
Affiliation:
1. Computer Engineering Research Laboratory (CERL), Department of Electrical & Computer Engineering, University of Missouri-Columbia, Kanas City, MO, 64110,
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Mechanics of Materials,Modelling and Simulation,Software
Link
https://www.tandfonline.com/doi/pdf/10.1080/02286203.1995.11760266
Reference15 articles.
1. A.J. Smith, Design of CPU cache memories, TENCON 87, Seoul, 1987, 1016–1025.
2. P.C.C. Yen, J.H. Patel, L E.S. Davidson, Shared cache for multiple-stream computer system, IEEE. Trans, on Computer; CSe(l), 1983.
3. M. Dubios & F. A. Briggs, Effect of cache coherency in multiprocessors, IEEE. Trant. on Computer: C-31(11), 1982.
4. W.C. Yen, D.W.L. Yen, k K.S. Fu, Data coherence problem in a multicache systems, IEEE Trant. on Computer., C-54(l), 1985.
5. L.M. Censier & P. Feautrier, A new solution to coherence problem in multicache systems, IEEE. Trans, on Computers, C-27(12), 1978.
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