Model and physical implementation of multi-port PUF in 65 nm CMOS
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2012.687189
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1. Effect of glitches against masked AES S-box implementation and countermeasure
2. Short Pulse Generation With On-Chip Pulse-Forming Lines
3. Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
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