CNTFET-based design of multi-bit adder circuits
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2016.1253781
Reference22 articles.
1. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
2. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region
3. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking
4. Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale
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1. Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design;WSEAS TRANSACTIONS ON SYSTEMS;2024-04-09
2. A high-efficiency Wallace tree based multi-trit multiplier in CNTFET technology;International Journal of Electronics;2022-05-19
3. Design of a Full Swing 20-Transistors Full Adder Cell based on CNTFET with High Speed and Low PDP;2022 30th International Conference on Electrical Engineering (ICEE);2022-05-17
4. CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications;Journal of Circuits, Systems and Computers;2021-08-28
5. A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM;Microelectronics Journal;2021-05
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