Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Author:

Lu Shyue-Kung1,Yeh Fu-Min2,Shih Jen-Sheng1

Affiliation:

1. Department of Electronic Engineering, Fu Jen Catholic University, Taipei, Taiwan

2. Electronics Systems Division, Chung-Shan Institute of Science and Technology, Taipei, Taiwan

Abstract

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17

2. Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture;IEEE Transactions on Dependable and Secure Computing;2014-07

3. The survivability of design-specific spare placement in FPGA architectures with high defect rates;ACM Transactions on Design Automation of Electronic Systems;2013-03

4. Fault tolerance and reliability in field-programmable gate arrays;IET Computers & Digital Techniques;2010-05-01

5. JHDL Implementation of a BIST Scheme for Testing the Look-Up Tables of SRAM Based FPGAs;2006 49th IEEE International Midwest Symposium on Circuits and Systems;2006-08

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