Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/002072198134779
Reference24 articles.
1. An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices
2. An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating
3. Modeling of hot-carrier-stressed characteristics of nMOSFETs
4. Unified physical I-V model of fully depleted SOI/MOSFETs for analog/digital circuit simulation
5. Scaling constraints imposed by self-heating in submicron SOI MOSFET's
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Analytical modeling and simulation of a linearly graded binary metal alloy gate nanoscale cylindrical MOSFET for reduced short channel effects;Journal of Computational Electronics;2014-04-16
2. Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application;IEEE Transactions on Electron Devices;2012-12
3. Analytical I–V model of SOI and SON MOSFETs: a comparative analysis;International Journal of Electronics;2011-11
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