Towards a Formal Treatment of Logic Locking

Author:

Beerel Peter,Georgiou Marios,Hamlin Ben,Malozemoff Alex J.,Nuzzo Pierluigi

Abstract

Logic locking aims to protect the intellectual property of a circuit from a fabricator by modifying the original logic of the circuit into a new “locked” circuit such that an entity without the key should not be able to learn anything about the original circuit. While logic locking provides a promising solution to outsourcing the fabrication of chips, unfortunately, several of the proposed logic locking systems have been broken. The lack of established secure techniques stems in part from the absence of a rigorous treatment toward a notion of security for logic locking, and the disconnection between practice and formalisms. We seek to address this gap by introducing formal definitions to capture the desired security of logic locking schemes. In doing so, we investigate prior definitional efforts in this space, and show that these notions either incorrectly model the desired security goals or fail to capture a natural “compositional” property that would be desirable in a logic locking system. Finally we move to constructions. First, we show that universal circuits satisfy our security notions. Second, we show that, in order to do better than universal circuits, cryptographic assumptions are necessary.

Publisher

Universitatsbibliothek der Ruhr-Universitat Bochum

Subject

General Earth and Planetary Sciences,General Environmental Science

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. From Full-Custom to Gate-Array ASIC for Hardware IP Protection;2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS);2024-04-19

2. Logic Locking over TFHE for Securing User Data and Algorithms;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. On the Security of Sequential Logic Locking Against Oracle-Guided Attacks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

4. Logic Locking in Future IC Supply Chain Environments;Understanding Logic Locking;2023-09-23

5. Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

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