Author:
D’Silva Hansel Desmond,Kumar Amit
Publisher
Springer Nature Singapore
Reference48 articles.
1. Acito B (2019) Leveraging the best of package and IC design for system enablement. In: 2019 international wafer level packaging conference (IWLPC). IEEE, San Jose, CA, USA, pp 1–4. https://doi.org/10.23919/IWLPC.2019.8914109
2. AMD EPYC™ 9004 series processors. https://www.amd.com/en/partner/4th-generation-amd-epyc
3. Addressing memory performance for 100G ethernet networking. https://www.chipestimate.com/Addressing-Memory-Performance-for-100G-Ethernet-Networking/Memoir-Systems/Technical-Article/2012/09/18
4. Ansys electronics-electromagnetic, signal integrity, thermal and electro-mechanical simulation solutions. https://www.ansys.com/en-in/products/electronics
5. Chen S, Li C, Chen Y, Zhang W, Zhong J, Cai J (2015) Study on electrical performance of stacking die package with silicon interposer. In: 2015 16th international conference on electronic packaging technology (ICEPT). IEEE, Changsha, China, pp 1158–1161. https://doi.org/10.1109/ICEPT.2015.7236785