Efficiently Running SpMV on Multi-core DSPs for Banded Matrix-Reference-Cited by-同舟云学术

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Efficiently Running SpMV on Multi-core DSPs for Banded Matrix

Published:2024 Issue: Volume: Page:201-220
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:en
Short-container-title:

Author:

Bi Deshun,Li Shengguo,Zhang Yichen,Yang Xiaojian,Dong Dezun

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-97-0808-6_12

Reference41 articles.

1. Alappat, C., et al.: Performance modeling of streaming kernels and sparse matrix-vector multiplication on A64FX. In: IEEE/ACM PMBS, pp. 1–7. IEEE (2020)

2. Bell, N., Garland, M.: Implementing sparse matrix-vector multiplication on throughput-oriented processors. In: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, pp. 1–11 (2009)

3. Chen, L., Jiang, P., Agrawal, G.: Exploiting recent SIMD architectural advances for irregular applications. In: IEEE/ACM CGO, pp. 47–58. IEEE (2016)

4. Chen, S., Fang, J., Xu, C., Wang, Z.: Adaptive hybrid storage format for sparse matrix-vector multiplication on multi-core SIMD CPUs. Appl. Sci. 12(19), 9812 (2022)

5. Crane, H., Jr., Gibbs, N.E., Poole, W.G., Jr., Stockmeyer, P.K.: Algorithm 508: Matrix bandwidth and profile reduction. ACM Trans. Mathematical Softw. (TOMS) 2(4), 375–377 (1976)

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1. Efficiently Running SpMV on Multi-Core DSPs for Block Sparse Matrix;2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS);2023-12-17

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