Design of 1-Bit FinFET Sum Circuit for Computational Applications-Reference-Cited by-同舟云学术

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Design of 1-Bit FinFET Sum Circuit for Computational Applications

Published:2021-08-03 Issue: Volume: Page:590-596
ISSN:2367-3370
Container-title:Advanced Techniques for IoT Applications
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Author:

Pittala Chandrashekar^ORCID,Vijay Vallabhuni^ORCID

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-4435-1_57

Reference19 articles.

1. Tirumalasetty, V.R., Machupalli, M.R.: Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications. Int. J. Electron. 106(4), 521–536 (2019)

2. Shams, A.M., Darwish, T.K., Bayoumi, M.A.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 10(1), 20–29 (2002). https://doi.org/10.1109/92.988727

3. Zhuang, N., Haomin, W.: A new design of the CMOS full adder. IEEE J. Solid-State Circuits 27(5), 840–844 (1992)

4. WU, X., Prosser, F.: Design of ternary CMOS circuits based on transmission function theory. Int. J. Electron. 65(5), 891–905 (1988)

5. Zimmermann, R., Fichtner, W.: Low-power logic styles: CMOS versus pass transistor logic. IEEE J. Solid-State Circuit 32(5), 1079–1090 (1997)

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