Electrical Performance of Single Gate and Double Gate MOSFET to Optimize the Gate Length-Reference-Cited by-同舟云学术

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Electrical Performance of Single Gate and Double Gate MOSFET to Optimize the Gate Length

Published:2021 Issue: Volume: Page:673-682
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
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Author:

Lalthlamuana James,Maity Niladri Pratap,Singh L. L. K.,Maity Reshmi

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-33-4909-4_52

Reference18 articles.

1. Moore G (1965) Cramming more components onto integrated circuits. Electron 38:114–117

2. Rana V, Ahmed G, Ramesh A, Das S, Singh P (2020) Diameter depended piezoresistive sensing performance of junctionless Gate-All-Around Nanowire FET. IEEE Trans Electron Dev 67(7):2884–2889

3. Li W, Woo J (2020) Vertical P-TFET with a P-Type SiGe Pocket. IEEE Trans Electron Devices 67(4):1480–1484

4. Maity NP, Maity R, Baishya S (2019) An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J Comput Electron 18:65–75

5. Ma J, Matioli E (2017) Slanted tri-gates for high-voltage GaN power devices. IEEE Electron Device Lett 38(9):1305–1308

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Dual Material Tri-Gate Schottky Barrier MOSFET;2022 International Conference on Electronics and Renewable Systems (ICEARS);2022-03-16

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